`timescale 1ns / 1ps
`include "const.v"
module mips(
    input clk,
    input reset,
    input interrupt,
    output [31:0] addr
    );


    wire [31:0] C_addr, C_PC, C_Dout, C_Din, D_DR0, D_DR1, D_DR2, D_DR3, D_DR4, D_DR5;
    wire C_MemWr;
    wire [5:0] D_MemWr;
    wire [1:0] C_store, D_store;
    wire C_int = 0;
    wire [5:0] IRQ;

    assign addr = C_PC;

    CPU cpu(
        .clk(clk), .reset(reset),
        .C_PC(C_PC), .C_addr(C_addr),
        .C_MemWr(C_MemWr), .C_store(C_store),
        .C_Dout(C_Dout), .C_Din(C_Din),
        .C_IRQ(IRQ)
        );

    Bridge bridge(
        .C_MemWr(C_MemWr), .C_addr(C_addr),
        .C_Din(C_Din),
        .D_MemWr(D_MemWr),
        .D_DR0(D_DR0), .D_DR1(D_DR1), .D_DR2(D_DR2), 
        .D_DR3(D_DR3), .D_DR4(D_DR4), .D_DR5(D_DR5)
    );



    TC tc0(
        .clk(clk), .reset(reset),
        .Addr(C_addr), .WE(D_MemWr[0]),
        .Din(C_Dout), .Dout(D_DR0),
        .IRQ(IRQ[0])
    );

    TC tc2(
        .clk(clk), .reset(reset),
        .Addr(C_addr), .WE(D_MemWr[1]),
        .Din(C_Dout), .Dout(D_DR1),
        .IRQ(IRQ[1])
    );

    assign IRQ[2] = interrupt;

    DM dm(    // device 0
        .clk(clk), .reset(reset), .en(D_MemWr[3]),
        .A(C_addr), .Din(C_Dout), .addr(C_PC),
        .DR(D_DR3), .store(C_store)
    );assign IRQ[3] = 0;

    assign IRQ[4] = 0;
    assign IRQ[5] = 0;

endmodule
